1. Field of the Invention
The present invention relates to integrated circuits and more particularly to logic integrated circuits used in MOS technology.
2. Discussion of the Related Art
Integrated circuits may include numerous internal components and access pads, each of which may transmit and/or receive logic and/or analog signals. More particularly, input pads capable of receiving logic signals will be considered, although the same pads can also operate as output pads depending on whether an input amplifier or output amplifier is selected.
FIG. 1 schematically shows a conventional input pad 10 connected through a metallization 17 to an input of an amplifier 11 that is integral with an integrated circuit. Pad 10 receives external logic signals, that is, voltages at a predetermined high or low level. Additionally, each pad is generally associated with overvoltage protection components, for example, electrostatic discharges. These protection components are not represented for the sake of simplification.
Pad 10 is connected outside the integrated circuit through a conductor 12. As indicated above, conductor 12 is normally set to a high or low voltage. However, in many situations, conductor 12 is allowed to float. Then, there is a risk that input amplifier 11 may receive this floating voltage either as a low level or as a high level. Moreover, parasitic pulses or electrostatic discharges occurring on conductor 12 modify the pad voltage and will cause undesirable changes to the input of amplifier 11.
Thus, users of logic integrated circuits usually provide means for fixing the voltage of the logic inputs to a predetermined quiescent level when the input is floating. In the whole description, it is assumed that this predetermined quiescent level is the high level. However, of course, the invention can be readily adapted by those skilled in the art to the case when this predetermined quiescent level is the low level.
Conventionally, users of logic integrated circuits place outside the input circuit a so-called pull-up resistor, here resistor 13, between the input conductor 12 and voltage Vdd corresponding to the high level. Resistor 13 must have a sufficiently high value in order not to cause an excessive current consumption when conductor 12 is set to the low level and must have a sufficiently low value so that the time required for eliminating a parasitic pulse, when conductor 12 is in the floating state, is short enough. A commonly adopted trade-off value is approximately 50 k.OMEGA.; however, this trade-off value is not fully satisfactory.
Additionally, the provision of a pull-up resistor placed outside the integrated circuit complicates the connections that are to be made by the user of the integrated circuit.